1. Statement of the Technical Field
The inventive arrangements relate to digital communication equipment using an error correction technique. More particularly, the inventive arrangements relate to a serial concatenated convolutional code decoder.
2. Description of the Related Art
A serially concatenated convolutional code (SCCC) decoder provides a means for recovering information bits from a codeword. A codeword is often comprised of a bitstream that has been encoded using a forward error correction (FEC) technique based on at least one convolutional code. A codeword may be a relatively large sequence of information bits (for example, a few thousand information bits) to provide a high recoverability of encoded information container therein.
It is known in the art that a plurality of SCCC decoders can be implemented in a parallel configuration on a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Each of the SCCC decoders is coupled to a respective random access memory (RAM) data store via a system bus. Each RAM data store contains data needed by a respective SCCC decoder to sequentially write sets of serially linked information bits to a depermutation and/or a permutation buffer memory for storage. Each RAM data store also contains data needed by a respective SCCC decoder to non-sequentially read sets of serially linked information bits from the depermutation and/or permutation buffer memory.
Each SCCC decoder is comprised of an input buffer memory, a processing loop module, and an output buffer memory. The input buffer memory is comprised of hardware and firmware configured to receive encoded information bits from an external device and to temporarily store the same. The processing loop module is comprised of hardware and firmware configured to decode information bits using an iterative process (described in greater detail below). In this regard, it should be appreciated that the processing loop module is often comprised of an inner decoder module, a depermutation module, an outer decoder module, and a permutation module. The output buffer memory is comprised of hardware and firmware configured to receive decoded information bits from the processing loop module and to temporarily store the same.
With regard to the processing loop module, the burden of decoding information contained within a codeword is split between the inner decoder module and the outer decoder module. In this regard, it should be appreciated that the inner decoder module and the outer decoder module employ methods of maximum a posteriori (MAP) decoding or max-log approximations to MAP decoding. MAP decoding and max-log approximations to MAP decoding are well known to persons skilled in the art. Thus, such methods will not be described in great detail herein.
The inner decoder module is often comprised of hardware and firmware configured to obtain a sequence of information bits from the input buffer memory and/or the permutation module. Upon receipt of all or a portion of an information bit sequence, the inner decoder module begins processing the received information bits. This processing typically involves performing a relatively simple decoding operation based on a corresponding convolutional inner code. After processing the information bits, the inner decoder communicates the processed information bits to the depermutation module for depermutation (i.e., rearrangement or reorganization) and storage in a depermutation buffer memory. In this regard, it should be understood that the depermutation of processed information bits is accomplished by reading the stored information bits from the depermutation buffer memory in an order different from an order in which the information bits were written to the depermutation buffer memory for storage. It should also be understood that depermutation of information bits is necessary to reverse a permutation of information bits that occurred in an encoding process.
The outer decoder module is comprised of hardware and firmware configured to receive a sequence of depermuted information bits communicated from the depermutation module. Upon receipt of all or a portion of an information bit sequence, the outer decoder module begins processing the received information bits. This processing typically involves performing a relatively simple decoding operation based on a corresponding convolutional outer code. After processing the information bits, the outer decoder module communicates the processed information bits to the permutation module for permutation (i.e., rearrangement or reorganization) and storage in a permutation buffer memory. It should be understood that permutation is necessary to realign the information bits to the permutation that occurred in an encoding process. The permutation of processed information bits is accomplished by reading the stored information bits from the permutation buffer memory in an order different from an order in which the information bits were written to the permutation buffer memory for storage. Thereafter, a sequence of permuted information bits is communicated, along with the original codeword, to the inner decoder module.
The above described process is performed for ‘M’ iterations. After ‘M’ iterations, the outer decoder module produces decoded information bits. Subsequently, the outer decoder module forwards the decoded information bits to the output buffer memory for storage.
As will be appreciated by a person skilled in the art, FPGAs and ASICs have limited hardware resources. The above-described decoding system employing a number of parallel processing SCCC decoders and associated RAM data stores is hardware resource intensive. As such, it is desirable to have a decoding system with a more efficient use of FPGA and/or ASIC hardware resources.